1. The Field of the Invention
The present invention relates generally to integrated circuits having fusible elements and connectors thereon, and more specifically to a method of reworking such integrated circuits.
2. Description of the Prior Art
In an integrated circuit having fuses, specifically PROMS, rework of the wafer could lead to reliability problems. Generally in the past, the wafers have been scrapped instead of reworked because of the potential reliability problems. In the manufacturing process of semiconductor device as illustrated in FIG. 1, the upper surface of a semiconductor wafer 10 is coated with an oxide layer 12 in which openings are formed for impurity deposition and diffusion into the substrate and for contact areas to the substrate. Sometimes phosphorus is specifically diffused into the surface of oxide layer 12 for improving the characteristics and the stability of the semiconductor device as well as diffusion incidently resulting during the fabrication of NPN bipolar devices. This is illustrated as region 14 wherein the concentration decreases with depth from the surface. The formation of the fuses and interconnects proceed by applying a layer 16 of fusible material on the surface which is delineated to produce the specific fusible elements. Next, the surface of the wafer is deglazed with an etchant to assure good contact to the substrate surface by the connector material. However, while the deglaze appears to be non-selective, it is not because the fuses 16 on the surface serve to mask the oxide underneath from the etchant attack. This results in a formation of a raised area 18 of oxide below the fuse 16. The fabrication is completed by applying a layer 20 of connector material and delineation of the same. The resulting structure is illustrated in FIG. 2.
In efforts to rework the wafer would generally include stripping or removing the connectors 20 and the fuses 16. This would result in a non-planar oxide surface as illustrated in FIG. 3 wherein the heavily doped phosphorus region 18 is raised compared to the remaining low phosphorus region of the remainder of oxide layer 12. It has been found that fuses reprocessed on the structure illustrated in FIG. 3 are virtually impossible to realign perfectly and consequently result in the structure of FIG. 4 with a new fuse 22 is misaligned relative to the raised oxide region 18. Fuses 22 formed on the stepped region 18 are undesirable since they pose the potential problem of only partially programming.
Thus, there exists a need to provide an inexpensive process for reprocessing the oxide layer of semiconductor wafers to allow reworking of fuses and connectors thereon to produce a high reliability product.